1. Technical Field
The present invention relates to a method of fabricating a semiconductor device and a semiconductor device fabricated thereby and, more particularly, to a method of fabricating a semiconductor device by forming a diffusion barrier layer selectively and a semiconductor device fabricated thereby.
2. Discussion of the Related Art
With the trend toward an ever-increasing level of integration in semiconductor devices, the technology of multi-layered metal interconnects has become widely employed. In particular, multi-layered metal interconnects are preferably formed of a metal layer having low resistivity and high reliability, in order to improve the performance of the semiconductor device. A copper layer is generally used for the metal layer. However, it is difficult to pattern the copper layer through a typical photolithography process. Therefore, a damascene process is widely used as a technology for patterning the copper layer.
The damascene process is widely used to form an upper interconnect, which is electrically connected to a lower interconnect. The upper interconnect fills a groove formed inside an interlayer insulating layer. The groove is formed across an upper surface of a metal plug by patterning the interlayer insulating layer using a photolithography process. Further, the damascene process is used to form the metal plug. That is, a via hole is formed to expose a predetermined portion of the lower interconnect, and the metal plug is formed to fill the via hole. This damascene process of forming the metal plug and the upper interconnect is referred to as a “single” damascene process.
Alternatively, a damascene process can be used to form the metal plug and the upper interconnect at the same time. That is, a via hole, which exposes a predetermined portion of the lower interconnect, and a groove, which intersects an upper portion of the via hole, are formed at the same time. An upper interconnect is formed to fill the via hole and the groove. This damascene process is referred to as a “dual” damascene process.
Further, copper atoms have a high diffusion rate into an adjacent insulating layer or silicon layer. Thus, during the damascene process, the copper atoms are diffused into the insulating layer, thereby causing a leakage current, and are diffused into an active elements such as a transistor, thereby operating as impurities. Therefore, it is necessary to form a diffusion barrier layer in order to limit diffusion of copper from the copper layer forming the metal plug and/or the upper interconnect. The diffusion barrier layer prevents the copper atoms from being diffused into the insulating layer. However, the diffusion barrier layer, which is interposed between the lower interconnect and the metal plug and/or between the upper interconnect and the metal plug, increases via resistance.
A method of decreasing via resistance by removing a diffusion barrier layer between a metal plug and an interconnect layer is disclosed in U.S. Pat. No. 6,559,061, “Method and apparatus for forming improved metal interconnects” to Hashim, et al. The method disclosed by Hashim, et al. includes a process of depositing a diffusion barrier layer inside a hole confined inside an insulating layer on a copper feature. The process includes a deposition of a diffusion barrier layer on the surface of the hole. The diffusion barrier layer and the naturally formed oxide layer on at least one portion of the copper feature are removed, thereby exposing the at least one portion of the copper feature. According to the method, the diffusion barrier layer is formed on the surface of the holes, and the diffusion barrier layer is removed on the copper feature under the hole. As a result, the copper layer filling the hole and the copper feature are in direct contact with each other, thereby reducing via resistance.
However, the method is difficult to employ when forming the upper interconnects using the single damascene process. That is, the diffusion barrier layer is deposited inside a groove confined into the insulating layer on the metal plug. Then, the diffusion barrier layer on the metal plug is removed, thereby exposing the metal plug. At this time, the insulating layer adjacent to the metal plug is also exposed. Then, a copper interconnect is formed to fill the groove. The copper interconnect is in direct contact with the insulating layer adjacent to the metal plug. Thus, copper atoms can be diffused from the copper interconnect filling the groove into the insulating layer adjacent the metal plug.
Further, with increased integration semiconductor devices, the line width of the metal interconnect is reduced. The reduction of the line width of the lower interconnect leads to a size reduction in the via hole. The reduction of the line width of the lower interconnect reduces the process margin for aligning the via hole with the lower interconnect. Thus, the via hole can be formed at a lateral position that is beyond the width of the lower interconnect, thereby exposing the insulating layer adjacent to the lower interconnect. As a result, an unlanded via is formed, in which the metal plug makes contact with the insulating layer adjacent to the lower interconnect. The unlanded via is more likely to be formed when the size of the via hole cannot be further reduced, despite the reduction of the line width of the metal interconnect due to the higher integration. Thus, it is necessary to form a diffusion barrier layer for preventing metal atoms from being diffused into the insulating layer adjacent to the lower interconnect from the metal plug. However, the diffusion barrier layer cannot be formed between the metal plug and the insulating layer adjacent to the lower interconnect according to the method disclosed in the U.S. Pat. No. 6,559,061. Therefore, the method disclosed in the U.S. Pat. No. 6,559,061 does not provide a solution which leads to a reduction of via resistance and, at the same time, prevents diffusion of copper atoms when forming the copper interconnect using a single damascene process. Further, the process does not prevent metal atoms from being diffused from an unlanded via into the insulating layer adjacent the lower interconnect.